1. Field of the Invention
The present invention relates to electrically programmable read only memory devices, and more particularly to a method and apparatus for improved programming threshold voltage distribution.
2. Background Information
The fabrication of erasable programmable read only memories (EPROMs) utilizing metal-oxide-semiconductor (MOS) technology is well known in the art. The EPROMs employ an array of memory cells utilizing floating gates which are generally formed from polysilicon members completely surrounded by an insulator. Electrical charge is transferred into the floating gate using a variety of techniques such as avalanche injection, channel injection, Fowler-Nordheim tunneling, etc. EPROMs are erased by various phenomena including exposing the memory array to ultraviolet radiation to remove the charge. Electrically erasable read only memories (EEPROMs) were developed to provide the capability of electrically erasing programmed memory cells. Typically, each cell of an EEPROM comprises two or more transistors and can be individually erased. Another type of electrically erasable floating gate memory which uses a single transistor per cell is the "flash" EPROM, wherein the entire array, or an entire block of memory cells is electrically erased at a time.
FIG. 1 shows a portion of a flash memory array employing a typical NOR type architecture. In this array, a plurality of cells, for example sixteen cells, are arranged in a row. One such row 100 a comprises memory cells C101a-C116a. It will be appreciated that each row can comprise a greater or lesser number of cells. A second row 100b of cells C101b-C116b is also shown. Each cell, such as cell C101a comprises drain D101a, floating gate FG101a, source S101a, and control gate CG101a. Each drain in the array has its own contact, and the drains of each column of cells (e.g., cells C101a, C101b, etc.) are coupled in parallel by an overlying metal layer. In this array, the source is a single, elongated diffusion region, shared by all cells in the row. That is, cells C101a-C116a share a common source. Additionally, as can be seen from the Figure, this source diffusion region is also shared by row 100b immediately below. As shown, each row shares common ground contacts 110a and 110b on both sides of the source diffusion. The common ground contact is utilized to save area compared with an architecture wherein each source has a ground contact. While the diffusion region is conductive, it has a sufficiently high resistance such that a significant voltage drop occurs between each cell when a current flows. This resistance is illustrated by individual resistors in the Figures. It will be understood that the resistors are present for illustration purposes only, and are used to represent the resistance between each cell along the source diffusion. The resistance between each cell is typically in the range of approximately 80-150.OMEGA.. Typically, the two V.sub.ss lines shown are shorted together and coupled to ground.
In order to program one of the cells, for example cell C101a, a programming voltage, of, for example, 10-12 volts is applied to control gate CG101a via contact 115a, while a voltage of approximately 5-7 volts is applied to drain D101a, while source S101a is grounded. Note that none of the other cells in row 100a will be programmed, because no voltage is applied to their drains. Similarly, cell C101b or other cells in the same column as C101a will not be programmed, because no programming voltage is applied to their control gate 115b, and thus these transistors are off.
One problem that occurs in an array such as that shown in FIG. 1 is known as the series resistance effect along the source diffusion, which causes the programming threshold voltage and the read current to be non-uniform across an array. The series resistance effect arises because the resistance, and therefore the voltage drop, between a source and ground varies depending upon a cell's position in the row. Therefore, the potential difference during programming varies from cell to cell. For example, when programming cell C101a, with a given control gate and drain voltage, the potential difference between the control gate CG101a and source S101a, and between drain D101a and source S101a will depend upon the potential of the source, which in turn depends upon the programming current and the resistance between source C101a and ground. Assuming for purposes of illustration, that the resistance between each cell and between the end cells and the ground contact has a value of R, the equivalent resistance between source S101a and ground, Req, is ##EQU1## For a cell in the middle, such as cell C108a, the equivalent resistance will be much greater, as there is a resistance of 8R and 9R between cell C108a and ground contacts 110a and 110b, respectively, for an equivalent resistance of approximately 4.24R. Thus, the voltage drop between the source and ground is over four times as great for cell C108a as for C101a. Therefore, the source of cell C101a is at a lower potential (i.e., closer to ground) than the source of cell C108a. Thus, the potential difference between control gate CG101a and source S101a, and the potential difference between drain D101a and source S101a, will be greater than the corresponding potential differences between control gate CG108a and source S108a, and between drain D108a and source S108a of cell C108a, for example. This decreased potential difference, particularly the control gate-source potential difference, of the cells in the middle, such as cell C108a, causes the floating gates of such cells to be charged to a lesser level than the floating gate of cell C101a, for example. This results in a larger threshold voltage and smaller read current for the cells farthest from the ground contacts. In practice, in an army having 16 cells in a row with two ground contacts, the difference in threshold voltage between a cell in the middle and one immediately next to the ground can vary in the range of approximately 0.5-1 Volt. Thus, one cell may be sensed to fall into one logic state while another cell is sensed to fall into another logic state, even though both are programmed with the same voltages on the control gate and drain. This is particularly important in multi-level cell architecture, where the floating gates are programmed to several different levels so that each cell can be used to store more than a single bit of information. In such a case, the threshold voltage between levels is considerably less than in a cell having only two states, and the difference in threshold voltage due to the series resistance effect is even more likely to cause a cell to be sensed in the wrong logic state. Additionally, cells that are programmed to higher threshold voltages, for example, the cells next to the V.sub.ss line, have more electrons on the floating gate, and, therefore, have a higher internal field after these cells are programmed. This high internal field will tend to pull electrons out of the floating gate and cause charge loss. This charge loss is a reliability concern in devices that store information in the form of electric charge such as floating gate MOS devices.
What is needed is a method and device to minimize the series resistance effect, so that every cell sees the same series resistance during programming and read. The method and device should provide for a more uniform threshold voltage distribution which is particularly desired in multi-level cell architecture. It is further desirable that the method and device provide for programming of several logic states in a cell, utilizing a single programming voltage.